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GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
January 2000 Revised February 2000
GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
General Description
The GTLP17T616 is a 17-bit registered bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the LVTTL CLKAB. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down high impedance for live insertion s External VREF pin for receiver threshold adjustability s BiCMOS technology for low power dissipation s Bushold data inputs on A Port eliminates the need for external pull-up resistors for unused inputs s LVTTL compatible Driver and Control inputs s Flow-through architecture optimizes PCB layout s Open drain on GTLP to support wired-or connection s A Port source/sink -24 mA/+24 mA s B Port sink capability +50 mA s D-type flip-flop, latch and transparent data paths s GTLP Buffered CLKAB signal available (CLKOUT) s -40C to +85C Temperature operation
Ordering Code:
Order Number GTLP17T616MEA GTLP17T616MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
(c) 2000 Fairchild Semiconductor Corporation
DS500327
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GTLP17T616
Pin Descriptions
Pin Names Description OEAB OEBA CEAB CEBA LEAB LEBA VREF CLKAB CLKBA A1-A17 B1-B17 CLKIN CLKOUT A-to-B Output Enable (Active LOW) (LVTTL levels) B-to-A Output Enable (Active LOW) (LVTTL levels) A-to-B Clock/LE Enable (Active LOW) (LVTTL levels) B-to-A Clock/LE Enable (Active LOW) (LVTTL levels) A-to-B Latch Enable (Transparent HIGH) (LVTTL levels) B-to-A Latch Enable (Transparent HIGH) (LVTTL levels) GTLP Input Threshold Reference Voltage A-to-B Clock (LVTTL levels) B-to-A Clock (LVTTL levels) A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B Open Drain Outputs (GTLP Levels) B-to-A Buffered Clock Output (LVTTL levels) GTLP Buffered Clock Input/Output of CLKAB (GTLP Levels)
Connection Diagram
Truth Table (Note 1)
Inputs CEAB X L L X X L L OEAB H L L L L L L LEAB X L L H H L L CLKAB X H or L H or L X X A X X X L H L H Z B0 (Note 2) B0 (Note 3) L H L H Clocked storage of A data H L L X X B0 (Note 3) Clock inhibit Latched storage of A data Transparent Output B Mode
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. Note 2: Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Note 3: Output level before the indicated steady-state input conditions were established.
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GTLP17T616
Functional Description
The GTLP17T616 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) enable all 17 bits. The output enables (OEAB and OEBA) control the 17 bits of data and the CLKOUT/CLKIN buffered clock path. For A-to-B data flow, when CEAB is low, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are high impedance. The data flow of B-to-A is similar except that CEAB, OEBA, LEBA and CLKBA are used.
Logic Diagram
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GTLP17T616
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC ) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 5) DC Output Sink Current into A Port IOL DC Output Source Current from A Port IOH DC Output Sink Current into B Port in the LOW State, IOL DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V ESD Rating Storage Temperature (TSTG) -50 mA >2000V -65C to +150C -50 mA 100 mA -48 mA 48 mA -0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V
Recommended Operating Conditions
Supply Voltage VCC /VCCQ Bus Termination Voltage (VTT) GTLP VREF Input Voltage (VI) on A Port and Control Pins on B Port HIGH Level Output Current (IOH) A Port LOW Level Output Current (IOL) A Port B Port Operating Temperature (TA) +24 mA +50 mA -40C to +85C -24 mA 0.0V to VCC 0.0V to VCC 1.47V to 1.53V 0.98V to 1.02V 3.15V to 3.45V
Note 4: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions in not implied. Note 5: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL VREF VTT VIK VOH A Port B Port Others B Port Others B Port B Port VTT > VREF + 50 mV VTT > VREF + 50 mV VCC = 3.15V VCC = Min to Max (Note 7) VCC = 3.15V VOL A Port B Port II Control Pins A Port B Port IPU/PD IOFF II(hold) IOZH IOZL ICC (VCC/VCCQ) ICC (Note 8) A Port and Control Pins All Ports All Ports A Port A Port B Port A Port B Port A or B Ports VCC = 3.45V IO = 0 VI = VCC or GND VCC = 3.45V, A or Control Inputs at VCC or GND VCC = 3.45V VCC = Min to Max (Note 7) VCC = 3.15V VCC = 3.15V VCC = Min to Max (Note 7) VCC = 3.45V VCC = 3.45V VCC = 0 to 1.5V VCC = 0 VCC = 3.15V VCC = 3.45V II = -18 mA IOH = -100 A IOH = -18 mA IOH = -24mA IOL = 100 A IOL = 24mA IOL = 40 mA IOL = 50 mA VI = 3.45V or 0V VI = 3.45V or 0V VI = 0 to 3.45V VI/VO = 0 to 3.45V VI or VO = 0 to 3.45V VI = 0.8V VI = 2.0V VO = 3.45V VO = 1.5V VO = 0V VO = 0.55V Outputs HIGH Outputs LOW Outputs Disabled One Input at 2.7V 0 75 -75 10 5 -10 -5 45 45 45 2 mA mA VCC -0.2 2.4 2.2 0.2 0.5 0.4 0.55 5 10 5 30 30 V V A A A A A A A A V 0.25 VREF + 50 mV 1.0 1.5 Test Conditions Min VREF + 0.05 2.0 0.0 VREF - 0.05 0.8 VCC - 1.2V VCC -1.2 V Typ (Note 6) Max VTT Units V V V
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GTLP17T616
DC Electrical Characteristics
Symbol Ci Control Pins A Port B Port
(Continued)
Typ (Note 6)
Test Conditions VI = VCC or 0 VI = VCC or 0 VI = VCC or 0
Min
Max 5.0 7.0 9.0
Units
pF
Note 6: All typical values are at VCC = 3.3V, VCCQ = 3.3V, and TA = 25C. Note 7: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 8: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol fTOGGLE fMAX tWIDTH tSU Max Toggle Frequency Max Clock Frequency Pulse Duration Setup Time Test Conditions Transparent Mode Registered Mode LEAB or LEBA HIGH CLKAB or CLKBA HIGH or LOW A before CLKAB B before CLKBA A before LEAB B before LEBA CEAB before CLKAB CEBA before CLKBA tHOLD Hold Time A after CLKAB B after CLKBA A after LEAB B after LEBA CEAB after CLKAB CEBA after CLKBA Min 125 125 3.0 3.0 0.6 1.2 0.5 1.3 1.4 1.2 0 0.2 0.2 0 0.5 0.6 ns ns Max Unit MHz ns
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GTLP17T616
AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted).
CL = 30 pF for B Port and CL = 50 pF for A Port.
Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tRISE tFALL tRISE tFALL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH, tPZL tPHZ, tPLZ
Note 9: All typical values are at VCC = 3.3V, and TA = 25C.
From (Input) A LEAB CLKAB CLKAB
To (Output) B B B CLKOUT
Min 1.6 1.0 1.5 0.9 1.6 1.0 2.6 1.7
Typ (Note 9) 4.0 2.5 3.9 2.3 4.0 2.4 5.2 3.4 4.3 2.0 2.3 1.6 2.3 2.3
Max 6.3 4.4 6.3 4.2 6.3 4.0 7.7 6.0 6.5 4.3
Unit ns ns ns ns
OEAB
B or CLKOUT
1.1 1.0
ns ns ns
Transition time, B outputs (20% to 80%) Transition time, B outputs (80% to 20%) Transition Time, A outputs (10% to 90%) Transition Time, A outputs (90% to 10%) B LEBA CLKBA CLKOUT A A A CLKIN 1.7 1.7 0.3 0.4 0.5 0.6 1.2 2.2 OEBA A or CLKIN 0.3 0.3
2.9 3.2 2.5 2.5 2.6 2.8 2.4 3.5 2.8 2.5
4.5 5.8 4.6 4.6 4.6 4.6 5.3 5.3 5.2 5.2
ns ns ns ns
ns
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GTLP17T616
AC Extended Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port.
Symbol tOSLH (Note 11) tOSHL (Note 11) tPVHL (Note 12)(Note 13) tOSLH (Note 11) tOSHL (Note 11) tPVHL (Note 12)(Note 13) tOSLH (Note 11) tOSHL (Note 11) tOST (Note 11) tPV (Note 12) tOSLH (Note 11) tOSHL (Note 11) tOST (Note 11) tPV (Note 12) tPVHL (Note 11)(Note 12) tPDELLH (Note 14) tPDELHL (Note 14)
Note 10: All typical values are at VCC = 3.3V, and TA = 25C. Note 11: tOSHL/tOSLH and tOST - Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 12: tPV - Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 13: Due to the open drain structure on GTLP outputs tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values on the backplane. Note 14: tPDELLH and tPDELHL -B to CLKOUT propagation delay delta is defined as the difference between the CLKAB to CLKOUT propagation delay and the CLKAB to B propagation delays. This parameter is for a given device and is not meant to guarantee the delta between the CLKAB to CLKOUT propagation delays of one device and the CLKAB to B propagation delays of other devices. This parameter is guaranteed by design and statistical process distribution.
From (Input) A A CLKAB CLKAB B B B CLKBA CLKBA CLKBA CLKAB B
To (Output) B B B B A A A A A A CLKOUT CLKOUT
Min
Typ (Note 10) 0.3 0.3 0.3 0.3 0.3 0.3 0.5 0.3 0.3 0.5
Max 1.0 0.6 2.5 1.0 0.6 2.5 0.5 0.5 1.2 2.5 0.5 0.5 1.2 2.5 2.8
Unit ns ns ns ns ns ns ns ns ns ns ns ns
0 0
1.7 1.5
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GTLP17T616
Test Circuits and Timing Waveforms
Test Circuit for A Outputs Test Circuit for B Outputs
Test tPLZ/tPZL
S 6V
tPLH/tPHL OPEN tPHZ/tPZH GND
Note A: CL includes probes and Jig capacitance. Note B: For B Port, C L = 30 pF is used for worst case.
Voltage Waveform - Propagation Delay Times
Voltage Waveform - Pulse Width
Voltage Waveform - Setup and Hold Times
Voltage Waveform Enable and Disable times
Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output. Output Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output.
Input and Measure Conditions A or LVTTL Pins VinHIGH VinLOW VM VX VY VCC 0.0 VCC/2 VOL + 0.3V VOH - 0.3V B or GTLP Pins 1.5 0.0 1.0 N/A N/A
All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50 The outputs are measured one at a time with one transition per measurement.
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GTLP17T616
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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